Interupt request cycles

An interupt request cycle is basically a read access to the device with the only difference, that the CPU uses no /CS and therefore the chip selects have to be decoded out of the address bus. Instead of a chip select the device looks for a signal with the same meaning on its /IACK port. Figure illustrates the access.

  

Figure: <

tex2html_comment_mark> Timing of a interupt acknowledge cycle

The differences in respect to the timing analysis only come only through a little later start of the access out of the view from the busmaster device. Because the /IACK has to be decoded out of the address bits, the activating edge of /IACK is a little later than an ordinary /CS would be. But this makes the setup conditions on that edge even more relexed and the hold time conditions have never been a problem. More precisely, we get

$$\begin{eqnarray*}10 = t_{avcl} &<& t_{avsa} + t_{pd}^-(i,o)[GAL] = (16,11,9)\\ (10,0) = t_{wlcl} &<& t_{raaa} + t_{pd}^-(i,o)[GAL] = (16,11,11)\\ \end{eqnarray*}$$

Consequently, the device will generate a later response to that starting edge, i.e.

$$\begin{eqnarray*}& & t_{cs}^+ + t_{cldl} + 2 \cdot t_{pd}^+(i,o)[GAL] + t_{aist}... ...,19) > (343.4,684.4)\\ &\Rightarrow& i = ((6,7,8)(11,14,17))\\ \end{eqnarray*}$$

The rest of the access is completely congruent to the read access.