Write accesses

Figure illustrates the read access graphically.

Since the RW signal is registered in the GAL to function as WROE, it has to fulfill setup and hold times to the end of S1.

t_rw⁺ + t_s[GAL] < T

$$\Rightarrow (60,50,40) = T > t_{chrl}^+ + 7.0 = (36,30,26)$$

As the RW signal is valid during the whole cycle, the hold time is obviously obeyed.

We determine now, when the inner data bus DB is at latest stable. The WROE is valid after the first CPU clock.

t_wroe⁺ = T + t_pd(ck,o)[GAL] = T + 7.0

At the data bus interface chip there are now 3 concurrent paths, i.e. from the WROE enableing the output, from the WSEL switching to input port (instead of internal register) and the propagation from input to output port.

$$\begin{eqnarray*}t_{db}^+ = max \{ && t_{as}^+ + t_{pd}^+(s,o)[abt652], \\ && t... ...^+(oe,o)[abt652],\\ && t_{dat}^+ + t_{pd}^+(i,o)[abt652] \} \\ \end{eqnarray*}$$

  

Figure: Timing of a write access

With $T \ge 40$ the it follows that the last term determines the maximum. Thus,

t_db⁺ = 3/2 T + t_clsa - t_dvsa + 6.7

Now, we are ready to investigate the setup times at the activating edge of /CS. For the addresses and the RW signal we get

$$\begin{eqnarray*}10 = t_{avcl} &<& t_{cs}^- - t_{adr}^+ = (63,52,41)\\ (10,0)= t_{wlcl} &<& t_{rasa} = (70,54,40)\\ \end{eqnarray*}$$

Since the time, when the inner data bus DB is at latest stable is determined by the propagation delay of the ABT652, this reduces the minimum time span between data bus stable and activation of the /CS.

(0,-261) = t_dvcl < t_dvsa - t_pd⁺(i,o)[abt652] = t_dvsa - 6.7 = (8.3,3.3,1.3)

At the same time, the value of the data bus is stored in the internal register of the ABT652. Therefore,

$$t_s[abt652] < t_{dvsa} + t_{pd}^-(i,o)[GAL] \Leftrightarrow (15,10,8) = t_{dvsa} > ... - 1.0$$

The hold time is again obviously fulfilled.

For the recognition of the activation of /DACK the same equation hold as in the case of a read access.

At the end of the write access, addresses, the RW signal and data have to be held stable until after the hold time of the busmaster devices, i.e.

$$\begin{eqnarray*}(0,?) = t_{chai} &<& t_{snai} = (15,10,8)\\ 0 = t_{chwh} &<& t_{snrn} = (15,10,10)\\ ? = t_{chdi} &<& t_h(db)\\ \end{eqnarray*}$$

With the disactivating edge of /CS the data bus interface is switched to its internal register. This allows to hold the internal data bus until the next CPU starts

$$\begin{eqnarray*}t_h(db) &=& min \{ t_{as}^- , t_{wroe}^- \}\\ &=& \{ T/2 + t_{... ...+ t_{pd}^-(ck,o)[GAL] \}\\ &=& T/2 + t_{clsa}^- = (32,25,20)\\ \end{eqnarray*}$$

For the disableing of /DACK the same equation hold as in the case of a read access.