Read accesses

Figure illustrates the read access graphically.

At the activating edge of /CS addresses and the RW signal have to be stable a certain time before.

$$\begin{eqnarray*}10 = t_{avcl} &<& t_{avsa} = (15,10,8)\\ (10,0) = t_{wlcl} &<& t_{raaa} = (15,10,10)\\ \end{eqnarray*}$$

A method to guarantee the setup time for the PCD8584 in th case of a 25MHz CPU would delay the /CS artificially. Since this is a setup time and a worst case analysis, we can also state the following. In normal cases, i.e. proper power supply, decent ambient temperature, the worst case will never happen. If it happens the CPU speed will be reduced slightly.

For the recognition and proper save of the data value, there are two times relevant: the time when the data bus is stable and the time when /DACK is stable on the external bus.

The data bus driver ABT652 and the /DACKO output of the GAL are enabled with the /CS. Since it takes quite a while until the busmaster device generates a response, only the propagation delays of the interface logic is of interest. In a bus cycle without wait states, /DACK will be clocked at the beginning of S3 whereas the data bus will be latched at the beginning of S5. With i the number of wait state cycles, the following has to be obeyed. For the data bus it is

$$\begin{eqnarray*}& & t_{dat}^+ + t_{dicl} < (5/2 + i) T\\ &\Leftrightarrow& t_{... ...40) - (25,23,19) > (191.7,188.7)\\ &\Rightarrow& i = (2,3,4)\\ \end{eqnarray*}$$

and for the /DACK signal it is

$$\begin{eqnarray*}& & t_{cs}^+ + t_{cldl} + t_{pd}^+(i,o)[GAL] + t_{aist} < (3/2 ... ...,19) > (336.7,677.7)\\ &\Rightarrow& i = ((6,7,8)(11,14,17))\\ \end{eqnarray*}$$

  

Figure: Timing of a read access

At the disableing edge of /CS there are 3 limitations. First, the data bus has to be stable until after the hold time of the CPU port. Second, the data bus and the /DACK signal must not be actively driven until after the disable time of the CPU (which is roughly the start of the next cycle).

The data bus is hold until the data bus interface chip is disabled through the GAL.

0 = t_sndi < t_pd^-(i,o)[GAL] + t_dis^-[abt652] = 1.0 + 1.3 = 2.3

At latest the data bus is disabled after the maxmimum times in the equation above.

(55,48,45) t_shdi > t_pd⁺(i,o)[GAL] + t_dis⁺[abt652] = 10.0 + 8.5 = 18.5

With the same edge also the /DACK is disabled. The disable time of the output port of the GAL is enlarged by a small $\epsilon$ due to the pullup resistor.

$$(80,60,50) = t_{sndn}^+ > t_{dis}^+[GAL] + \epsilon = 9 + \epsilon$$