Timing of the accesses to the external busmasters

The accesses to external devices are mainly determined by two signals - the chip select (/CS) and the data acknowledge (/DACK). An access runs basically in 3 steps:

1.

The CPU starts the access by preparing all necessary signals on the bus and then pulling /CS low.

2.

The external device stores the data from the data bus or puts valid data on the data bus and indicates that itself is ready now in pulling /DACK low.

3.

The CPU finishes the access in disableing /CS again. It expects the device to disable its /DACK and its data bus interface soon thereafter.

Out of this observation, the analysis of the timing will be divided into 3 time points, too. At the first point, there are limitations due to the setup times to the activating edge of /CS, i.e. for the addresses, the RW signal and in case of a write also for the data.

From the activating of /CS results a propagations delay for the activating edge of /DACK. This gives the basis for the calculation of the number of wait states. At the same time, there are setup and hold time limitations to a certain edge of the internal clock of the CPU in the case of read accesses.

At the third point, the disableing of /CS, the device has to obey a disable time of /DACK and the data bus in case of a read. In case of a write, there are hold time limitations of the device for addresses, data and the RW signal.

Before we verify all the limitating equations in detail, we first compute some basic time points, that a common to all cases.

 

Table: Bus timing specification of the MC68332

Symbol	Characteristic	16.78MHz		20.93MHz		25.17MHz
		min	max	min	max	min	max
tchav	clock high to address, FC valid	0	29	0	23	0	19
tclsa	clock low to /as, /ds, /cs asserted	2	25	0	23	0	19
tavsa	address, FC valid to /as, /cs asserted	15	-	10	-	8	-
tclsn	clock low to /as, /cs, /ds negated	2	29	2	23	2	19
tsnai	/as, /ds, /cs negated to address, FC invalid	15	-	10	-	8	-
tsnrn	/as, /ds, /cs negated to rw negated	15	-	10	-	10	-
tchrl	clock high to rw low	0	29	0	23	0	19
traaa	rw asserted to /as, /cs asserted	15	-	10	-	10	-
trasa	rw low to /ds, /cs asserted (write)	70	-	54	-	40	-
tchdo	clock high to data out valid	-	29	-	23	-	19
tsndoi	/ds, /cs negated to data out invalid	15	-	10	-	5	-
tdvsa	data out valid to /ds, /cs asserted (write)	15	-	10	-	8	-
tdicl	data in valid to clock low	5	-	5	-	5	-
tsndn	/as, /ds negated to /dsack negated	0	80	0	60	0	50
tsndi	/ds, /cs negated to data in invalid	0	-	0	-	0	-
tshdi	/ds, /cs negated to data in High-Z	-	55	-	48	-	45
taist	asynchronous input setup (/dsack)	5	-	5	-	5	-
tradc	rw asserted to data bus impedance change	40	-	32	-	25	-

Table gives a summary of all used timing information of the CPU. Since there are 3 types of CPU possible in the system, there are 3 columns with the respective figures.

For the symbols in the equations, we introduce the following notation. The minimum propagation delay is always denoted with a minus sign, whereas the maximum with a plus sign. Where necessary the pair of input and output port meant is given in round brackets and the subscript 'pd' is used. Setup times (with the subscript 's') are always maxmimum times and hold times (with the subscript 'h') are always minimum times. Where necessary the input signal meant is given in round brackets. Disable times are handled like propagation delays. To avoid naming conflicts, the device name to which the time refers is given in square brackets.

In starting an access to an external device the CPU prepares the bus, i.e. it drives address bus and RW signal in the first half of the first CPU cycle (S0).

$$\begin{eqnarray*}t_{adr} &=& t_{chav}\\ t_{rw} &=& t_{chrl}\\ \end{eqnarray*}$$

In the second half of the first CPU cycle (S1), valid addresses and a valid RW signal are indicated by activation of /AS.

t_as = T/2 + t_clsa

For a read access the chip select follows the /AS signal ( t_cs := t_as), whereas it follows the /DS signal for write accesses ( t_cs := t_ds). The indication of valid data through activation of /DS happens in the second half of the second CPU cycle (S3).

t_ds = 3/2 T + t_clsa

In this case the data bus is valid at latest at

t_dat⁺ = t_cs⁺ - t_vdsa^- = 3/2 T + t_clsa⁺ - t_vdsa^-

In order to keep the following investigation clear, we divide it further into the two cases read access and write access.

 

Table: Timing specifications of the embedding logic

Symbol	Characteristic	min	max
GAL22V10DQP
tpd(i,o)	input valid to output valid	1	10
tpd(ck,o)	clock to output valid	1	7
ts	data setup to clock	-	7
th	data hold to clock		-
ten	input to output enabled	1	10
tdis	input to output disabled	1	9
ABT652
tpd(i,o)	input valid to output valid	1.5	6.7
tpd(sel,o)	select valid to output valid	1.5	7.7
tpd(ck,o)	clock to output valid	1.7	8.4
ts	data setup to clock	-
th	data hold to clock		-
ten	/oe to output enabled	1.3	8.5
tdis	/oe to output disabled	1.5	8.2
ALS518
tpd(i,o)	input valid to output valid	3	33
ABT16823
ts(ck)	data setup to clock	-
th(ck)	data hold to clock		-
ts(en)	setup en to clock	-
th(en)	hold en to clock		-

Table gives all necessary specifications of the embedding logic. Table summarizes all the timing limations that have to be verified for the single busmaster devices.

 

Table: Timing specifications of the busmaster devices

Symbol	Characteristic	PCD8584		SCN68681		XR68C192
		min	max	min	max	min	max
tavcl	address valid to /cs low	10	-	10	-
twlcl	rw valid to /cs low	10	-	0	-
tdvcl	data valid to /cs low	0	-	-261	-
tchai	/cs high to address invalid	0	-
tchwh	/cs high to rw high	0	-	0	-
tchdi	/cs high to data invalid
tcldl	/cs low to /dtack low	-	325	-	666
tchdh	/cs high to /dtack high		120		100
tcldv	/cs low to data valid		180		175