Timing of the accesses to the binary output register

The access to the fast binary output register ABT16823 is a simple write access to a memory mapped device, i.e. the clock enable for the register is decoded directly from the address bus. The register is clock with the disableing edge of /DS. So, the setup time is determined by the difference of the earliest disableing of /DS and the latest time, when data is valid.

t_s[abt16823] < T - t_chdo⁺ + T/2 + t_clsn^-

The hold time is guarantied by the minimum data hold time of the CPU

t_h[abt16823] < t_sndoi^-

The more critical observation is, whether the clock enable signal is valid in time and is disabled again before the next CPU cycle starts.

In order to determine the timing of the clock enable, we distinguish two cases: the earliest CPU cycle i^- and the latest CPU cycle i⁺where the GAL might produce a valid clock enable. Thus,

$$\begin{eqnarray*}max \{ t_{as}^- , t_{rw}^- , t_{eq}^- , t_{adr}^- \} + t_s[GAL]... ... , t_{rw}^+ , t_{eq}^+ , t_{adr}^+ \} + t_s[GAL] &\le& i^+ T \\ \end{eqnarray*}$$

with t_eq^- = t_adr^- + t_pd^-[als518] and t_eq⁺ = t_adr⁺ + t_pd⁺[als518]. Since the minimum propagation delay of the ALS518 is very short the earliest cycle is clearly determined by the address strobe. Because $T/2 \ge 20$ and t_as^- certainly less than T/2 - 7.0 it follows that

i^- = 1

A similar observation yields to the result

i⁺ = 2

With these precalculations the timing of the clock enable is now fixed to

$$t_{regce}^- = T + 1.0 \quad ; \quad t_{regce}^+ = 2T + 7.0$$

In order to guarantee proper operation the latest clock enable has to be earlier than the earliest clock, which is /DS.

$$t_{regce}^+ < t_{ds}^- \Leftrightarrow 2T + 7 < 5/2 T + t_{clsn}^- \Leftrightarrow T/2 > 7 - t_{clsn}^-$$

The same observation as for the enableing holds also for the disabling, i.e. the disableing is certainly before the next active edge of /DS.