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00016 #include <cubeos.h>
00017 #include <kerror.h>
00018 #include <fastbin.h>
00019 #include <mc68681.h>
00020 #include <mc68332.h>
00021 #include <tpud.h>
00022 #include <io_duart.h>
00023 #include <hw_drivers.h>
00024
00025 #define MAXFB 16
00026
00034 struct fb_info {
00035 char type;
00036 char id;
00037 };
00038
00043 struct fb_info fbs[MAXFB];
00044
00045 unsigned int _FBIN_ttlfastbin_state;
00046 unsigned int FBIN_rcjfastbin_state;
00047
00055 int FBIN_init ()
00056 {
00057 int i;
00058
00059
00060 for (i = 1; i < MAXFB; i++) {
00061 fbs[i].type = FBTYPE_EMPTY;
00062 fbs[i].id = 0;
00063 }
00064 RCJ_init ();
00065 RG_init ();
00066
00067 return 0;
00068 }
00069
00098 int FBIN_make (int nr, char type, char id)
00099 {
00100
00101
00102 if (nr >= MAXFB)
00103 return (-1);
00104 fbs[nr].type = type;
00105 fbs[nr].id = id;
00106
00107 switch (type) {
00108 case FBTYPE_DUART:
00109
00110
00111 #ifdef DUART_BASE
00112 switch (id) {
00113 case 2:
00114 DUART_clearOPCR (0);
00115 DUART_clearOPCR (1);
00116 break;
00117 case 3:
00118 DUART_clearOPCR (2);
00119 DUART_clearOPCR (3);
00120 break;
00121 case 4:
00122 case 5:
00123 case 6:
00124 case 7:
00125 DUART_clearOPCR (id);
00126 break;
00127 default:
00128 fbs[nr].type = FBTYPE_EMPTY;
00129 return (-1);
00130 }
00131 #else
00132 return -1;
00133 #endif
00134 break;
00135 case FBTYPE_TPU:
00136
00137 TPU_makedio (id);
00138 TPU_setdio (id, 0);
00139 break;
00140 case FBTYPE_TTL:
00141
00142 #ifdef FASTBIN_BASE
00143 if (FASTBIN_BASE == 0) {
00144 fbs[nr].type = FBTYPE_EMPTY;
00145 KERN_complain (ERR_WARN, "Trying to use fastbin register without any register around");
00146 return (-1);
00147 } else {
00148
00149 writeshort (FASTBIN_BASE, 0);
00150
00151 _FBIN_ttlfastbin_state = 0;
00152 }
00153 #else
00154 fbs[nr].type = FBTYPE_EMPTY;
00155 KERN_complain (ERR_WARN, "Trying to use fastbin register without any register around");
00156 return (-1);
00157 #endif
00158 break;
00159 case FBTYPE_CPU:
00160
00161 switch (id) {
00162 case FBCPU_PCS1:
00163 writebyte (SPI_QPDR, readbyte (SPI_QPDR) & 0xEF);
00164 writebyte (SPI_QPAR, readbyte (SPI_QPAR) & 0xEF);
00165 writebyte (SPI_QDDR, readbyte (SPI_QDDR) | 0x10);
00166 break;
00167 default:
00168 fbs[nr].type = FBTYPE_EMPTY;
00169 return (-1);
00170 }
00171 break;
00172 case FBTYPE_RCJ:
00173
00174 if (id > 7) {
00175 fbs[nr].type = FBTYPE_EMPTY;
00176 return (-1);
00177 }
00178 #ifdef RCJFB_BASE
00179 if ((RCJFB_BASE) == 0) {
00180 fbs[nr].type = FBTYPE_EMPTY;
00181 KERN_complain (ERR_WARN, "Trying to use rcj fastbin register on non-rcj hardware");
00182 return (-1);
00183 } else {
00184
00185
00186 writebyte (RCJFB_BASE, 0);
00187
00188 FBIN_rcjfastbin_state = 0;
00189 }
00190 #else
00191 fbs[nr].type = FBTYPE_EMPTY;
00192 KERN_complain (ERR_WARN, "Trying to use rcj fastbin register on non-rcj hardware");
00193 #endif
00194 break;
00195 default:
00196 return (-1);
00197 }
00198
00199 return (0);
00200
00201
00202 }
00203
00211 int FBIN_set (int i, char v)
00212 {
00213 char type, id;
00214
00215 type = fbs[i].type;
00216 id = fbs[i].id;
00217 switch (type) {
00218 case FBTYPE_DUART:
00219 #ifdef DUART_BASE
00220 switch (id) {
00221 case 2:
00222 if (v) {
00223 setDUARTOPR (2);
00224 } else {
00225 clearDUARTOPR (2);
00226 }
00227 break;
00228 case 3:
00229 if (v) {
00230 setDUARTOPR (3);
00231 } else {
00232 clearDUARTOPR (3);
00233 }
00234 break;
00235 case 4:
00236 if (v) {
00237 setDUARTOPR (4);
00238 } else {
00239 clearDUARTOPR (4);
00240 }
00241 break;
00242 case 5:
00243 if (v) {
00244 setDUARTOPR (5);
00245 } else {
00246 clearDUARTOPR (5);
00247 }
00248 break;
00249 case 6:
00250 if (v) {
00251 setDUARTOPR (6);
00252 } else {
00253 clearDUARTOPR (6);
00254 }
00255 break;
00256 case 7:
00257 if (v) {
00258 setDUARTOPR (7);
00259 } else {
00260 clearDUARTOPR (7);
00261 }
00262 break;
00263 default:
00264 return -1;
00265
00266 }
00267 #else
00268 return -1;
00269 #endif
00270 break;
00271 case FBTYPE_TPU:
00272 TPU_setdio (id, v);
00273 break;
00274 case FBTYPE_TTL:
00275 if (v) {
00276 _FBIN_ttlfastbin_state |= (1 << id);
00277 } else {
00278 _FBIN_ttlfastbin_state &= (~(1 << id));
00279 }
00280 #ifdef FASTBIN_BASE
00281 writeshort (FASTBIN_BASE, _FBIN_ttlfastbin_state);
00282 #endif
00283 break;
00284 case FBTYPE_CPU:
00285 switch (id) {
00286 case FBCPU_PCS1:
00287 if (v) {
00288 writebyte (SPI_QPDR, readbyte (SPI_QPDR) | 0x10);
00289 } else {
00290 writebyte (SPI_QPDR, readbyte (SPI_QPDR) & 0xEF);
00291 }
00292 break;
00293 default:
00294 return (-1);
00295 }
00296 break;
00297 case FBTYPE_RCJ:
00298
00299
00300 if (v) {
00301 FBIN_rcjfastbin_state |= ((1) << id);
00302 } else {
00303 FBIN_rcjfastbin_state &= (~(1 << id));
00304 }
00305
00306 #ifdef RCJFB_BASE
00307 writebyte (RCJFB_BASE, FBIN_rcjfastbin_state);
00308 #endif
00309 break;
00310 default:
00311 return (-1);
00312 }
00313 return 0;
00314 }