00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018 #define DUART_ADDR(nr) (DUART_BASE + nr)
00019
00020 #define DUART_MR1A DUART_ADDR(0x00) // Mode Register A
00021 #define DUART_MR2A DUART_ADDR(0x00) // Mode Register A
00022 #define DUART_SRA DUART_ADDR(0x01) // Status Register A
00023 #define DUART_CSRA DUART_ADDR(0x01) // Clock-Select Register A
00024 #define DUART_CRA DUART_ADDR(0x02) // Command Register A
00025 #define DUART_RBA DUART_ADDR(0x03) // Receive Buffer A
00026 #define DUART_TBA DUART_ADDR(0x03) // Transmit Buffer A
00027 #define DUART_IPCR DUART_ADDR(0x04) // Input Port Change Register
00028 #define DUART_ACR DUART_ADDR(0x04) // Auxiliary Control Register
00029 #define DUART_ISR DUART_ADDR(0x05) // Interrupt Status Register
00030 #define DUART_IMR DUART_ADDR(0x05) // Interrupt Mask Register
00031 #define DUART_CUR DUART_ADDR(0x06) // Counter Mode: current MSB
00032 #define DUART_CTUR DUART_ADDR(0x06) // Counter/Timer upper reg
00033 #define DUART_CLR DUART_ADDR(0x07) // Counter Mode: current LSB
00034 #define DUART_CTLR DUART_ADDR(0x07) // Counter/Timer lower reg
00035 #define DUART_MR1B DUART_ADDR(0x08) // Mode Register B
00036 #define DUART_MR2B DUART_ADDR(0x08) // Mode Register B
00037 #define DUART_SRB DUART_ADDR(0x09) // Status Register B
00038 #define DUART_CSRB DUART_ADDR(0x09) // Clock-Select Register B
00039 #define DUART_CRB DUART_ADDR(0x0A) // Command Register B
00040 #define DUART_RBB DUART_ADDR(0x0B) // Receive Buffer B
00041 #define DUART_TBB DUART_ADDR(0x0B) // Transmit Buffer A
00042 #define DUART_IVR DUART_ADDR(0x0C) // Interrupt Vector Register
00043 #define DUART_IP DUART_ADDR(0x0D) // Input Port
00044 #define DUART_OPCR DUART_ADDR(0x0D) // Output Port Configuration Reg.
00045 #define DUART_STRTCC DUART_ADDR(0x0E) // Start-Counter command
00046 #define DUART_OPRSET DUART_ADDR(0x0E) // Output Port Reg, SET bits
00047 #define DUART_STOPCC DUART_ADDR(0x0F) // Stop-Counter command
00048 #define DUART_OPRRST DUART_ADDR(0x0F) // Output Port Reg, ReSeT bits